Silicon on insulator (SOT) applications are commonly utilized where a high degree of noise isolation or low signal loss is required. In conventional SOI applications, a conducting inversion layer is typically present at an interface between a base oxide and a high resistivity handle wafer. Resistivity requirements imposed by active devices used in SOI applications also typically require a top semiconductor layer having a much lower resistivity than the high resistivity handle wafer. The combination of a low resistivity top semiconductor layer and an inversion layer at the base oxide-handle wafer interface results in a lossy, non-linear network that degrades isolation and linearity within SOI applications at high frequencies and power levels.
Attempts to provide a high degree of noise isolation and low signal loss in SOI applications have included forming high resistance portions of the handle wafer in isolation trenches at the interface between the base oxide and handle wafer. However, as the area available for isolation trenches within SOI applications decreases, the effectiveness of such narrow high resistance portions of the handle wafer also decreases.